Staff Engineer, FPGA

Samsung Semiconductor•San Jose, CA

13h•Onsite

About The Position

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Requirements

Bachelor’s with 10+ years, or Master’s with 8+ years, or PhD's with 5+ years of industry experience.
BS/MS in Electrical Engineering, Computer Engineering, or related field with 3-5+ years of industry experience in FPGA development, with a strong portfolio in high-performance digital design (More experienced candidates will also be considered at relevant levels).
Expertise in SystemVerilog, Verilog, and RTL design tools such as Xilinx Vivado, Intel Quartus and familiarity with simulation tools such as Questa, Xcelium, or VCS.
Strong computer architecture, memory coherency, and data structures fundamentals.
Deep understanding of AMBA (AXI/AXIS), PCIe, CXL.cache protocols and CXL Type-1/2 devices.
Strong analytical and troubleshooting skills to resolve complex hardware bottlenecks.
Must be highly motivated with excellent verbal and written communication skills, and ability to thrive in a collaborative, multi-disciplinary environment.

Nice To Haves

Prior experience in designing coherent memory systems and control path design for accelerators is a big plus.

Responsibilities

Develop and optimize RTL (SystemVerilog/Verilog) IPs for CXL Type-2 FPGAs, focusing on the CXL.cache controller, command queues and DMA management.
Design high-speed, cache-line-granular command queue interfaces to allow host CPUs to efficiently update device registers and control structures.
Implement hardware mechanisms to maintain coherent access between host CPU and FPGA, reducing synchronization latency and software overheads.
Optimize RTL to meet strict latency and bandwidth requirements, managing memory access patterns and improving the pipeline for high-speed operations.
Collaborate with software engineers to integrate with kernel drivers and user-space libraries.
Debug complex RTL-to-Host issues in a laboratory environment, using tools like logic analyzers, PCIe protocol analyzers, and CXL emulators.
Develop SystemVerilog testbenches and simulation models to verify protocol compliance and functional correctness, focusing on high-speed data processing.