Staff Engineer, DRAM

Samsung Semiconductor•San Jose, CA

10d•$163,000 - $253,000•Onsite

About The Position

The DRAM Design Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash. DDL’s vision is to solve key problems in developing next-generation DRAM solutions, including High Bandwidth Memory (HBM). We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is designing HBM product, developing DRAM architecture, co-working head office and managing customer in all stages of design. You’ll focus on enhancement of full chip sim check, DFT consultation, IDD / PDN / checking reliability by developing the architecture of DRAM and optimize it for mass production.

Requirements

Bachelors with 10+ years of relevant industry experience, or Masters with 8+ years or PhD with 5+ years of experience in DRAM or related technical field preferred.
Required knowledge, achievements, and skillsets in memory design.
Proficient with design software and statistical analysis tools.

Nice To Haves

Expertise in DRAM product development (DDRx, GDDRx, LPDDRx, HBMx, etc.)
Strong experience in DRAM I/O interfaces and SERDES
Proficiency in DRAM full chip functional verification
Comprehensive understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
Demonstrated track record of innovation and creativity in problem solving
You’re inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Responsibilities

Develop DRAM architecture and optimize floorplan for next generation DRAM
Lead design specification, performance analysis and test plan etc.
Technical interactions with internal and external customers
Develop ROW, Column Bank architecture design and related test modes
Develop methods to reduce DRAM power consumption
Analyze electrical data from Si and validate new core design architecture performance
Develop and implement a DFT architecture and methodology for the product
Power delivery network floor planning and optimization
Collaboratively design with cross-functional teams, such as product managers, engineers, and marketers, to ensure that designs align with the product vision and strategy
Identify device requirements for the advanced memory product design
Collaborate with process integration, quality assurance, product engineering and modeling group for DRAM design architecture and technology optimization