Staff Engineer, Design Verification Engineering

Analog Devices•Wilmington, MA

4d•Hybrid

About The Position

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Requirements

Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
OR Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Demonstrated Expertise (“DE”) using metric-driven verification throughout the full lifecycle of design/verification, including verification planning, test bench and test case development using System Verilog and UVM.
DE learning end application/systems and mapping into smart verification test plans.
DE translating Design Verification requirements such as test plans into a robust DV environment as well as architecting and analyzing coverage to drive convergence.
DE using UVM agents, and integrating third-party or custom Verification IPs (VIPs) to develop stimulus sequences and functional checkers within a UVM testbench.
DE debugging simulations and analyzing waveforms.

Responsibilities

Develop and execute UVM-based verification environments for block-level and full-chip ASIC/SOC designs.
Create and implement verification plans and strategies, including constrained-random and directed test cases.
Write and analyze functional coverage, assertions, and metrics to ensure thorough verification and track progress.
Integrate and verify third-party and custom IPs/VIPs within subsystem-level UVM environments.
Collaborate with design and cross-functional teams to review test plans, resolve issues, and ensure coverage closure.
Support post-silicon verification activities, working with evaluation and applications engineering teams.
Automate simulation data analysis and model validation using scripting languages and design automation tools.