Staff Engineer, Application Engineering

Marvell Technology•Santa Clara, CA

1d•$157,000 - $162,000

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Marvell's Optical and Copper Connectivity Business Unit is the industry leading provider of infrastructure solutions to enterprise, data center, service providers, small business, and digital home customers. The Ethernet PHY applications team is a key part of Optical and Copper Connectivity Business Unit that drives key design wins for 1-Gigabit, Multi-Gigabit, 10-Gigabit, up to 400-Gigabit Ethernet PHY products. We are looking for a customer facing passionate, experienced, hands-on engineer to bring us to greater heights. If you are an individual who is confident in his technical abilities and leads by example, we are looking for you. Our Application Engineers expected to have knowledge of SW programming and HW fundamentals as well as the curiosity and persistence to take on interesting and challenging issues on a daily basis.

Requirements

Master’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and two (2) years of experience in the job offered or related occupation.
Utilizing Matlab, Python, C/C++, or C# for data collection and validation.
Using Cadence Virtuoso, Allegro PCB tools, ADS, Visual Studio, and Hspice for circuit and system-level modeling.
Operating Oscilloscopes, BERTS (Bit Error Rate Testers), VNA, Spectrum Analyzer, and DCAs.
Optimizing and tuning CTLE, FFE, and DFE performance for PAM4 and NRZ signaling.
Hardware Bring-up and Debug: Root cause analysis of mixed-signal and firmware-hardware interaction issues in high-speed electrical interface.
Performing schematic and layout reviews for high-speed PCB and module designs (eg., OSFP, OSFP-XD, QSFP, QSFP-DD).
System-level design and compliance tests for Ethernet (for 112G, 224G and 448G) and PCIe (Gen5/6/7) standards.
Conducting S-parameter analysis, Time domain analysis, eye diagram capture, and link margin optimization for data center interconnects.
Performing host-module or switch side interoperability testing including link-training, auto-negotiation, and CMIS5.0 compliance tests.
Validating mixed-signal integrated circuits and Serdes IP High-Speed SerDes, PLL, ADC, power regulator, temperature sensor.

Responsibilities

Develop test plans and generate test reports.
Perform chip/system level IP application and support such as High-Speed SerDes, PLL, ADC, power regulator, temperature sensor.
Develop and execute bench-level validation test plans, develop scripts to automate testing, generate appropriate test reports, and write application issues.
Responsible for BU interface/SoC support project management/issue resolution schedule control and BU/customer relationship management.
Run CE internal project flow/execution optimization and improvement.
Support internal SoC, FAE, and ATE team on testing and system level debugging.
Provide direct technical support to top tier customers, including design review, problem discussion, and performance tuning to meet system requirements.
Act as a primary technical interface between company and customers.
Make new product recommendations to Design/Marketing teams.