Staff Digital Engineer

Renesas Electronics•Chandler, AZ

About The Position

This is an opportunity to join a top-notch Power Management IC Team with Renesas’ leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow’s automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital design team and work closely with the analog design team for design integration, as well as the applications and test engineering teams for validating and testing your on-chip solutions. You will have an opportunity to work on new designs, develop new standards and shape the company’s pathway for success.

Requirements

5-11+ Years experience in digital design
Bachelor degree is a must.
Must be a team player and yet be an independent thinker with strong design fundamentals
Must have experience of conceptualizing and creating robust and understandable designs
deal candidate will have solid understanding of synthesizable design, timing constraints and how their design implementation looks like on silicon.
Must have experience with industry standard tools atleast two from Synopsys, Cadence, Mentor, Siemens, etc..
Attention to detail, accuracy, and good communication skills
Must have good written, verbal, cross-functional, multi-site collaboration skills.
Have an analytical mind - be open to persuasion and have capability to persuade others

Responsibilities

Designing digital RTL that meet timing, area, power and any adhering standards specifications.
Integrating design at the top level and running block & top-level simulations.
Participate in all aspects of Mixed-signal design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.
Working closely with P&R team and supervising their work to generate a layout that meets timing, area, and power requirements.
Assisting with top level test-bench creation and running gate level simulations.
Working with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification.
Helping develop AMS, SystemVerilog or Verilog-real behavioral models for your circuits.
Developing detailed design documents and help writing chip level documents and collateral.
Holding and participating in key design reviews and completion of various checklists.