Staff Device Integration Engineer

Samsung•Austin, TX

1d•Onsite

About The Position

Samsung Austin Semiconductor (SAS) is seeking a highly driven candidate to join the Device Integration team. As a Device Integration Engineer, one will be responsible for the optimization of transistor performance and targeting to maximize product yield, reliability, and manufacturability on mass production as well as new and developing 14nm derivative generation. The ideal candidate would have Device physics interaction understanding across all modules – Fin/PC, SD, RMG/MOL, BEOL – in order to work closely with Module Integration and Process Architecture teams to develop ideal transistor performance and targeting conditions on current and next generation technologies. The role will also require detailed SRAM understanding at both design and verification stages.

Requirements

Bachelors of Science or Engineering (Electrical, Computer, Chemical, Material Science, or related areas) required.
8+ years of semiconductor industry experience is required; 10+ years of experience is highly preferred.
Demonstrated experience with technology, process & qualification development milestones in order to meet customer and industry specifications.
Understanding of the interactions between process and Electrical test.
Knowledge of process flow.
Familiarity with unit processes including thin films deposition, etch, diffusion, wet process, CMP, Photolithography, etc.
Analysis skills, including electrical device characterization, yield analysis, data mining, DOE, and SPC.
JMP or Spotfire.
SRAM design verification using simulation tools to ensure compliance with functional specifications and foundry design rules.
SPICE modeling/simulation and MHC experience.

Nice To Haves

Masters or PhD is a plus.

Responsibilities

Ensure targeting of transistor focused Electrical Test (ET) trends to Customer/Product Specifications and perform timely root cause study to shifts or abnormalities.
Analyze process interactions (inline metrology, FDC, etc.) to ET while also understanding ET data effects on Parametric Yield.
Owns Parametric Yield and Wafer Acceptance Electrical Test (WAT) management for one or more Customer Accounts/Products.
Execute and analyze experiments to optimize transistor performance/variation with end goal of improving Parametric Yield and ensuring a reliable and manufacturable product.
Drive Task Force Teams to solve systematic yield, performance, or reliability issues.
Support unit process (ex: CMP, Etch, etc) or process integration team with evaluation of device impact for key change points (ex: cost/step reduction, throughput improvement, etc.).
Conduct SRAM performance analysis, measuring speed, power, noise margin, and leakage across process corners and temperature ranges.