Staff Design Verification Engineer – CPU Core Formal Verification

SiFive•Austin, TX

About The Position

SiFive is looking for a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality. This is a Staff individual-contributor role within the CPU Design Verification organization, focused on applying formal methods to complex out-of-order CPU core microarchitecture. The role is aimed at an engineer who can independently own difficult verification problems, define strong property-driven verification strategies, identify risk early, and improve verification quality across the broader CPU DV effort. The primary technical scope includes formal verification of CPU core units such as frontend, midcore control logic, issue and commit behavior, load-store interactions, clock-gating and control logic, and other bounded or high-risk microarchitectural behaviors where exhaustive reasoning provides strong value. You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role.
Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture.
Strong hands-on experience with formal verification for RTL, including assertion-based verification, proof analysis, abstraction techniques, and closure of non-trivial properties.
Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
Strong debugging skills with the ability to root-cause issues across specification, RTL, properties, and verification infrastructure.
Strong understanding of verification methodology, including test planning, failure analysis, coverage thinking, and signoff discipline.
Familiarity with scripting or programming in Python, Perl, Tcl, or similar languages used for automation and infrastructure.
BS/MS Degree in EE, CE or CS
5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification
Deep understand of computer architecture is desired
Experienced developer using Object Oriented Programing principles

Nice To Haves

Experience with out-of-order CPU core verification.
Experience applying formal methods to CPU core areas such as frontend control, issue logic, scoreboarding, commit, LSU ordering behavior, MMU/TLB control, or power / clock-gating logic.
Experience with formal techniques for safety, liveness, deadlock, forward progress, connectivity, reset, and microarchitectural consistency checks.
Experience balancing formal and simulation approaches, including identifying when a problem is best solved through exhaustive proof versus dynamic verification.
Experience improving formal convergence through abstraction, environment modeling, assume-guarantee decomposition, and scalable proof planning.
Experience collaborating across architecture, RTL, formal, and design verification teams in a fast-moving CPU development environment.
Experience mentoring engineers and influencing verification methodology beyond immediate ownership scope.

Responsibilities

Own formal verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level proof strategy through signoff-oriented closure.
Develop formal verification plans based on architectural intent and microarchitectural risk, including assumptions, assertions, covers, abstraction strategy, and closure criteria.
Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure for complex CPU control, ordering, and interface behavior.
Target high-value CPU verification problems such as pipeline control, issue and dispatch correctness, flush and replay behavior, register/data movement correctness, load-store ordering, hazard handling, forward progress, and clock-gating correctness.
Use the right mix of abstraction, decomposition, bounded proofs, connectivity checks, X-prop style reasoning, and bug-hunting strategies to improve proof convergence and debug efficiency.
Analyze proof failures, counterexamples, vacuity, over-constraint, and incompleteness, and drive fixes across RTL, properties, assumptions, and verification infrastructure.
Partner closely with architecture, RTL, and simulation-focused DV engineers to review specifications, identify ambiguities early, and align formal results with broader verification goals.
Contribute reusable formal methodology, automation, debug workflows, and infrastructure that improve productivity and verification quality across future CPU core programs.
Mentor other engineers through reviews, property-quality guidance, and formal-debug best practices.