Staff CPU Microarchitect, Vector and Matrix Compute

Tenstorrent

1d•$100,000 - $500,000•Remote

About The Position

Tenstorrent is seeking an experienced CPU Architect/Micro-Architect to drive the next generation of high-performance RISC-V CPU Vector (RVV), Floating Point, and Matrix extensions. In this role, you will drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads. Working closely with architects, software teams, silicon designers, and external IP partners, you will translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms. This role is ideal for an architect/micro-architect who enjoys working across hardware and software boundaries, defining next-generation compute architectures, and shaping how CPUs and HPC/AI workloads work together. This role is remote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

5+ years of experience in CPU design for high-performance computing and AI acceleration.
Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads.
Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators.
Experience defining architectural specifications and leading cross-functional teams from concept through silicon implementation.
Experience with RTL development with cutting edge AI frontier models.
Passionate about designing next-generation compute architectures for AI, HPC, and large-scale datacenter systems.
Experienced in CPU architecture with strong knowledge of AI acceleration, matrix math, floating point, and heterogeneous compute systems.
Comfortable making architectural decisions across CPU cluster and subsystems.
Collaborative technical leader who enjoys influencing cross-functional engineering teams.
Curious and driven to solve challenging performance, scalability, and system architecture problems.

Nice To Haves

RTL design with cutting edge AI frontier models.

Responsibilities

Drive both the architecture and micro-architecture of compute execution units and subsystems that enable the efficient execution of modern high-performance computing (HPC), and AI inference/training workloads.
Translate HPC/AI workload requirements into scalable CPU architectures that optimize performance, power, and area (PPA) while enabling future HPC/AI computing platforms.
Define next-generation compute architectures.
Shape how CPUs and HPC/AI workloads work together.