Staff ATE Test Engineer

Google•Sunnyvale, CA

2d•$192,000 - $278,000

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Google’s data centers are some of the most advanced in the world. In this role, you will serve as a technical leader to build the SoCs that power these data centers by defining the strategy and architecture for comprehensive Automatic Test Equipment (ATE) test solutions in high-volume manufacturing. You will own the end-to-end silicon test life-cycle, establishing methodologies that close the loop between field performance, design, and testing for future generations of chips. You will lead cross-functional initiatives to integrate advanced SoC technologies into devices and architect robust ATE manufacturing tests that ensure optimal performance and yield. As a Staff Engineer, you will set the technical direction for test coverage and quality standards across the organization.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits Learn more about benefits at Google [https://www.google.com/about/careers/applications/benefits/].

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in test engineering, product engineering or silicon quality/reliability.
Experience in ASIC or SoC test development, bring-up or debug.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scan/ATPG test development or memory BIST test development and repair implementation.
Experience testing IPs such as Phase-Locked Loops (PLLs), PVT sensors, temperature sensors, Process Monitor Ring Oscillator (PMRO), and eFuse.
Experience with ATE probe card design and load board design.
Experience with UCIE, HBM, PCIE, DDR.
Extensive experience with Automatic Test Equipment (ATE) from Advantest and Teradyne (e.g., EXA scale, UltraFlex+).

Responsibilities

Lead the development and architectural definition of silicon test requirements, driving strategic alignment across design teams, DFT engineers, and external vendors.
Define and direct broad strategies for SoC product NPI, bring-up, verification, characterization, and qualification, resolving complex issues across bench testing, test-coverage optimization, and system-to-ATE correlation.
Act as a domain expert in ATE testing, leveraging deep industry experience to establish technical standards, architect scalable test solutions, and mentor engineering teams to drive systemic quality improvements.
Influence and partner strategically with design, DFT, and quality teams to shape next-generation chip architectures, ensuring proactive "design-for-testability" and establishing industry-leading best practices for post-silicon testing.
Oversee and optimize the chip production life-cycle, driving continuous improvement initiatives for test program architecture, advanced volume data analytics, test time reduction, yield optimization, and complex Return Merchandise Authorization (RMA) failure analysis.