Staff ASICS Physical Design Engineer
About The Position
This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of applying specialized and advanced knowledge in performing timing analysis of complex sub-systems from System-on-Chips (SoC) context and ensure timing closure across various operating modes and corners. Work on multiple complex premium tier chips implemented with most advance technology’s node, like 14nm, 5nm, 34nm, and 3nm. Apply expertise in various SoC design architecture. Design methodologies and timing signoff process. Responsibilities also include performing constraint validation at various levels of design stages, conducting various clock tree analyses, early planning of pipelines for critical interface timing closure, multiple flow/scripts development to easy access to timing reports, mentor and train junior team members, performing correlation activities between PNR tool and timing signoff tools with collaborating with multiple teams, and generating ECOs for various subsystems. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
Requirements
- Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
- Seven (7) years of progressive experience in a related occupation.
Responsibilities
- Performs timing analysis of complex sub-systems from System-on-Chips (SoC) context and ensure timing closure across various operating modes and corners.
- Works on multiple complex premium tier chips implemented with advanced technology nodes (14nm, 5nm, 34nm, and 3nm).
- Applies expertise in various SoC design architecture, design methodologies, and timing signoff processes.
- Performs constraint validation at various levels of design stages.
- Conducts various clock tree analyses.
- Plans pipelines for critical interface timing closure.
- Develops multiple flow/scripts to easily access timing reports.
- Mentors and trains junior team members.
- Performs correlation activities between PNR tool and timing signoff tools in collaboration with multiple teams.
- Generates ECOs for various subsystems.
- Acts as a strong contributor at design reviews and project meetings.
- Communicates and implements a development plan.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
