Staff Analog/Mixed Signal Engineer

Samsung Semiconductor•San Jose, CA

1d•$163,000 - $253,000•Onsite

About The Position

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams. Samsung Semiconductor Inc is looking for a talented Senior/Staff PLL Designer with strong background and hands-on experience in PLL and clock generation circuit design. The candidate will work on the design and development of high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies.

Requirements

Bachelor’s with 10+ years of experience or Master's with 8+ years of experiences or PhD with 5 years of experience in a related field.
Hands-on experience in designing various frequency synthesizer and clock generation circuits, such as VCO, DCO, charge-pump, analog or digital phase detector, regulators, bandgrap reference, reference clock oscillator and buffer, DLL, phase interpolator, etc. in deep sub-micron CMOS technologies.
Ability to comprehend PLL loop system knowledge to circuit level specifications.
Excellent problem solving and analytical skills are essential.
Strong knowledge on IC design CAD tools such as Spectre, SpectreRF, AMS simulator, Matlab.
Familiar Verilog, SystemVerilog programming.
A thorough understanding of the physical layout requirement and ability to perform the critical layouts.
Lab testing skills to evaluate the prototype unit to the design specification.
Motivated to carry out a wide variety of tasks with clear communication and presentation skills in a dynamic team environment.

Responsibilities

Design RF/Analog PLL and clocking circuits using advanced deep-submicron CMOS technologies.
Design Serdes analog PHY circuits using advanced deep-submicron CMOS technologies.
Perform system modeling and analysis for mixed signal system.
Perform design verification and production support tasks.
Work closely with digital and software developers to develop an implementation that meets system requirements.