Staff Analog Layout Engineer

Neurophos • San Mateo, CA

1d • Onsite

About The Position

We are seeking a seasoned Senior or Staff Analog Layout Engineer to play a vital role in developing cutting-edge full-custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will develop and optimize high-performance Analog IPs tailored for TSMC’s deep-submicron processes, including N12, N3P, and N2P. You will push the boundaries of Power, Performance, and Area (PPA) while mitigating the impact of Restricted Design Rules (RDRs) and electromigration.

Requirements

• B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a closely related discipline.
• 3-8+ years of professional custom or block-level IC layout experience in deep-submicron, advanced FinFET/GAA nodes (3nm, 2nm, etc.).
• Mastery of industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV).
• Deep understanding of deep-submicron layout techniques, parasitic reduction, matching strategies, and electro-migration (EM/IR).

Nice To Haves

• Prior tape-out success in TSMC N3 or N2 process nodes.
• Domain knowledge in laying out high-performance analog/mixed signal blocks, such as PLLs and Data Converters (ADC/DAC).
• Working knowledge of layout automation scripting languages (e.g., TCL, Perl, Python).

Responsibilities

• Perform custom IC layout execution of high-speed analog/RF circuits.
• Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions
• Deliver IP-level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and Latch-up prevention.
• Execute and debug block-level design sign-offs, including DRC (Design Rule Check), LVS (Layout Versus Schematic), and RC Extraction using standard industry tools.
• Evaluate layout trade-offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity.
• Coordinate directly with circuit designers, CAD engineers, and EDA vendors to ensure IP design fits seamlessly into the production flow.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching and stock option opportunities
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree