SSD Qualification Engineer - PCIe Validation

Everpure•Santa Clara, CA

19h•Onsite

About The Position

As a PCIe Validation Engineer (IC) on the Drive Qualification team, you will design and execute PCIe‑focused validation and debug for Everpure SSDs. You’ll own link and protocol test coverage, develop automated test suites and frameworks using PCIe analyzers and exercisers, and drive issues from first detection through root cause and closure. This is a hands‑on role with deep involvement in test development, lab debug, and cross‑functional collaboration.

Requirements

6+ years experience in SSD, storage, or PCIe‑centric validation / bring‑up (or equivalent embedded / high‑speed I/O domain).
Strong understanding of PCIe fundamentals.
Hands‑on experience using PCIe analyzers/exercisers (e.g., Teledyne/LeCroy, Keysight, or similar) for trace capture and debug.
Comfortable with Python (or similar) for test and tooling development.
Able to work effectively in Linux‑based validation environments.
Experience with CI / regression infrastructure (e.g., Jenkins, Git‑based workflows) for large‑scale test execution.
Strong debug skills across HW/FW/system boundaries; able to go from symptom to hypothesis to validated root cause.
Clear written and verbal communication, with the ability to present findings, trade‑offs, and recommendations to engineering and program teams.
Highly self‑motivated, detail‑oriented, and comfortable operating in a fast‑paced development environment.

Responsibilities

Define PCIe test plans covering link training, lane width/speed changes, resets, hot‑plug, surprise removal, error injection, power‑management states, and recovery behaviour.
Execute Gen4/Gen5/Gen6 link and protocol tests across different platforms and system configurations.
Validate SSD behaviour under abnormal and corner conditions.
Provide periodic PCIe validation readouts for critical program milestones.
Develop and maintain automated PCIe test suites.
Integrate PCIe analyzers, exercisers, and Quarch‑class tools into test frameworks to enable reproducible, automated scenarios.
Triage failures from regression, bring‑up, and customer scenarios; correlate PCIe traces, NVMe/OCP logs, and system logs.
Partner with FW, HW, and systems teams to root‑cause and verify fixes, and roll improvements back into the test suite.
Leverage PCIe analyzers/exercisers for trace capture, error injection.
Use oscilloscopes, logic analyzers, BERTs, and related tools (as needed) to support signal‑ and protocol‑level debug.
Lead coverage improvements based on lessons learned.
Standardize PCIe test APIs, logs, and reporting for reuse across products.
Share PCIe debug and test BKMs (Best Known Methods).