SRAM Mask Layout Designer

Qualcomm•Austin, TX

5d•$58 - $87

About The Position

Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm’s High-performance CPU Team as a SRAM Mask Layout Designer? You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics.

Requirements

15+ years of experience and a high school diploma or equivalent OR 12+ years experience and BS in Electrical Engineering OR 10+ years experience and MS in Electrical Engineering
Direct experience with custom SRAM layout
Experience in industry standard custom design tools and flows.
Knowledge of leading-edge FinFET processes (5nm or newer).
Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies.
Knowledge of all aspects of Layout floorplanning and hierarchical assembly.
Knowledge of Cadence Virtuoso and Calibre LVS/DRC.
Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
High School diploma or equivalent and 10+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
6+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

Nice To Haves

Good understanding of device parasitics and reliability considerations during layout.
Good understanding of critical circuits and layout styles.
Ability to write Skill code for layout automation.
Knowledge of improving EMIR in layout.
Good communication skills to work with different teams to accurately describe issues and follow them through for completion.

Responsibilities

Design layout for custom memories and other digital circuits based on provided schematics.
Read and interpret design rule manuals to create optimal and correct layout.
Own the entire layout process from initial floorplanning to memory construction to physical verification.
Use industry standard verification tools to validate LVS, DRC, ERC etc.
Interpret the results from the verification suite and perform layout fixes as needed.
Provide layout fixes as directed by the circuit design engineers.
Work independently and execute memory layout with little supervision.
Provide realistic schedules for layout completion.
Provide insight into strategic decisions regarding memory layout and area.