SRAM Design Engineer

NVIDIA•Santa Clara, CA

1d•$116,000 - $189,750

About The Position

The Digital IP (DIP) group at NVIDIA develops IP for every chip designed at NVIDIA. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.

Requirements

BSEE minimum (or equivalent experience), MSEE or PhD
2+ years of professional experience in SRAM design
Familiarity with Cadence Virtuoso schematic and layout capture tools
Willingness and ability to use AI effectively in day-to-day tasks

Nice To Haves

Self-motivation, attention to detail, and good written, verbal, and presentation skills are essential to success in this role
We rely heavily on AI coding and analysis tools such as Codex and Claude Code. The more developed your skills in this area, the better
Silicon testing and debugging experience

Responsibilities

Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
Advanced development: Exploring the potential of future process nodes and developing techniques to realize optimal power, performance, and area characteristics.
Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.