Sr Staff Validation Engineer
About The Position
Marvell is hiring a Senior Staff Validation Engineer to perform post-silicon validation of PCIe PHYs for storage devices. The role includes defining, documenting, executing, and reporting the overall PHY validation and test plan. The engineer will bring up silicon in the lab and execute unit tests focused on PCIe Physical and PCS layer hardware and firmware, extending validation to the PCIe protocol layer. The position involves high-speed signal validation and analysis, including measurement of eye diagrams, jitter, and bit error rates. The engineer will debug PHY protocol issues across storage interfaces such as SATA, SAS, PCIe, and Ethernet, using lab diagnostics and test equipment. The role also involves leading collaborative technical discussions, working with cross-functional teams and external vendors, and partnering with customers to resolve design issues and failure cases. The broader team validates amplifiers used to drive optical electronic devices and receivers, silicon photonics, and upper electronics, and supports the coherent digital signal processing unit. This is a specialized area involving technologies used by internal and external customers.
Requirements
- Strong understanding of high-speed SERDES, equalization techniques, and PCIe protocols.
- 8–10 years of experience with high-speed I/O testing, debugging, and validation.
- Strong hands-on laboratory skills in system bring-up, system testing, and debugging.
- In-depth working knowledge of SERDES characterization test equipment, such as oscilloscopes, BERTs, and network analyzers.
- Strong analytical, problem-solving, and communication skills.
- Preferred education and experience: Bachelor of Science in Electrical Engineering with 8–10 years of relevant work experience, or Master of Science in Electrical Engineering with 3–5 years of relevant work experience.
Nice To Haves
- Working knowledge of PCIe interface characterization.
- Experience with Ethernet and/or SAS/SATA SERDES.
- Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces.
- Working knowledge of board design and ability to read board schematics and layouts.
- Knowledge of SERDES modeling techniques.
- Working experience with Perl or Python.
Responsibilities
- Take responsibility for PCIe PHY validation in a post-silicon environment.
- Define, document, execute, and report the overall PHY validation and test plan for Marvell storage devices.
- Perform lab-based silicon bring-up and unit testing of PCIe Physical and PCS layer hardware and firmware, extending testing to the PCIe protocol layer.
- Perform high-speed signal validation and analysis, measuring eye diagrams, jitter, and bit error rates.
- Analyze and debug PHY protocol issues involving SATA, SAS, PCIe, and Ethernet storage interfaces.
- Troubleshoot failing tests using diagnostics, software tools, hardware analyzers, oscilloscopes, meters, and logic or protocol analyzers.
- Lead collaborative technical discussions to drive resolution of technical issues.
- Work with cross-functional teams and external vendors to debug post-silicon and customer issues related to PCIe PHY.
- Work closely with customers to address design issues and debug failure cases.
Benefits
- Eligibility to participate in bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
- Employee stock purchase plan with a 2-year look back.
- Family support programs to help balance work and home life.
- Mental health resources.
- Recognition and service awards.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
