Sr. Staff Validation Engineer

Marvell•Santa Clara, CA

1d•$127,630 - $191,200

About The Position

Execute silicon bring-up and validation test plans for ASIC/SoC products with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces. Set up and maintain lab test environments, including boards, power supplies, clocks, resets, and cabling, to ensure stable and repeatable measurements. Operate lab equipment such as oscilloscopes, logic analyzers, protocol analyzers (PCIe/CXL), pattern generators, BERTs, power supplies, and environmental chambers. Develop and use scripts (Python, TCL, shell, MATLAB or similar) for lab automation and data collection/analysis. Run experiments to characterize link and memory behavior (e.g., throughput, latency, BER, margins, power) and summarize results. Assist in debugging issues across silicon, firmware, board, and test setup; capture logs, traces, and measurement data for senior engineers. Document test procedures, lab setups, and results; provide clear, concise updates to the validation lead and cross-functional teams. Contribute feedback to improve test plans, lab infrastructure, and validation processes.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (or equivalent experience).
4+ years of experience in silicon or system validation, hardware test, or related lab-based roles.
Working knowledge of high-speed interfaces and memory subsystems (e.g., PCIe, CXL, DDR, HBM, SerDes concepts).
Hands-on experience with lab instruments (oscilloscope, logic analyzer, protocol analyzer, power supplies, etc.).
Experience with at least one scripting language used in lab environments (e.g., Python, TCL, shell).
Strong problem-solving skills and attention to detail in executing tests and recording results.

Nice To Haves

Experience with validation or test of high-speed digital interfaces (PCIe, CXL, DDR, HBM or SerDes-based links).
Exposure to first silicon bring-up or early hardware prototyping.
Familiarity with version control and issue tracking tools used in engineering.

Responsibilities

Execute silicon bring-up and validation test plans for ASIC/SoC products with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces.
Set up and maintain lab test environments, including boards, power supplies, clocks, resets, and cabling, to ensure stable and repeatable measurements.
Operate lab equipment such as oscilloscopes, logic analyzers, protocol analyzers (PCIe/CXL), pattern generators, BERTs, power supplies, and environmental chambers.
Develop and use scripts (Python, TCL, shell, MATLAB or similar) for lab automation and data collection/analysis.
Run experiments to characterize link and memory behavior (e.g., throughput, latency, BER, margins, power) and summarize results.
Assist in debugging issues across silicon, firmware, board, and test setup; capture logs, traces, and measurement data for senior engineers.
Document test procedures, lab setups, and results; provide clear, concise updates to the validation lead and cross-functional teams.
Contribute feedback to improve test plans, lab infrastructure, and validation processes.