Sr Staff System Engineer

Renesas Electronics•San Jose, CA

22h•$160,000 - $235,000•Hybrid

About The Position

Applicants for this position must be currently authorized to work in the United States on a full-time basis. Renesas is unable to sponsor applicants for work visas for this position now or in the future. This role may sit in San Jose, CA; Phoenix, AZ; or Chandler, AZ (local candidates to these cities preferred - no relocation). This role sits within our Low-Voltage GaN Marketing & Systems Group, acting as a Sr Staff System Engineer to define the future of our power semiconductor portfolio. In this strategic role, you will not simply support existing products—you will be the technical authority responsible for driving next-generation IC product definition, silicon architectures, and long-term roadmap strategy. By leveraging deep expertise in low-voltage (<400V) BLDC and PMSM motor control, you will identify market gaps across high-growth applications (robotics, humanoids, e- mobility, power tools) and translate complex system-level challenges into actionable silicon-level requirements to deliver highly differentiated, system-optimized products.

Requirements

Deep theoretical and practical knowledge of Field-Oriented Control (FOC) using Clark/Park/Inverse transforms to control current/torque, velocity/position; and Space Vector Modulation (SVM) to translate the vectors calculated by the FOC algorithms into precise PWM control signals.
Experience with sensors and algorithms used for rotor angle acquisition and calibration.
Proficiency with model-based design using Mathworks (Matlab, Simulink, Simscape), Saber, PLECS, or PSIM to simulate motor dive system. Alternatively experience with co-simulation of the mechanical and electrical system using a combination like Simplis for the power inverter and Simulink for the motor mechanics and control.
Experience selecting and designing motor driver systems using integrated gate drivers and discrete power stages (MOSFETs, IGBTs, or Wide-Bandgap SiC/GaN devices)
Experience designing integrated circuits with focused drivers and related circuitry like slew rate control, current sensing, short circuit protection, high voltage level shifting, bootstrap, and charge pump supplies. Strong knowledge basic infrastructure and communications blocks like current/voltage references, level shifters, SPI, I2C, registers, e-fuse, amplifiers, and comparators.
Experience designing motor control systems with focus on managing thermal dissipation, optimizing efficiency, and managing EMC.
Experience designing motor control hardware that can withstand fault conditions like short-circuit, open-circuit, over/under voltage, sudden loss of power, and over temperature.
Advanced knowledge of PCB layout optimization for high-power switching, including minimizing parasitic inductance, mitigating EMI/EMC, and managing thermal dissipation (via thermal vias, or heatsinks).
Experience characterizing motors and optimizing motor control and protection utilizing motor control hardware and software together with standard lab equipment and a motor test stand
5-7+ years of experience in power electronics, semiconductor systems, or motor drive design, with a proven track record of successfully defining and launching motor control ICs or discrete power solutions to market.
Solid understanding of power semiconductor physics, specifically comparing Wide Bandgap (WBG) materials like GaN against silicon MOSFETs, including gate charge (Qg), reverse recovery (Qrr), and parasitic inductances.
BS in Electrical Engineering, Power Electronics, or a related field required; MS or PhD preferred.
Exceptional cross-functional collaboration and communication skills, with the ability to confidently present complex architectural concepts to both internal executive stakeholders and external customer engineering teams.

Responsibilities

Translate system-level application requirements into detailed IC specifications (e.g., Rds-on targets, gate drive source/sink strength, dead-time control, protection features like OCP/OTP, packaging thermal constraints, and monolithically integrated features).
Develop and influence future chip architectures based on system-level understanding of GaN-based power stage and driver IP and and sensing topologies. Drive the multi-year technology roadmap aligned with emerging market trends.
Collaborate closely with IC Design, R&D, and Marketing teams to ensure silicon implementation matches application realities. Balance system performance, silicon die area, cost targets, and time-to- market.
Design, schematic-capture, layout, and validate high-power-density system-level prototypes and evaluation boards (EVBs) to showcase GaN's superior switching performance under real- world operating conditions.
Perform rigorous technical trade-off analyses, worst-case circuit simulations, and competitive benchmarking to quantify GaN’s value proposition at the system level.
Support key tier-1 customer engagements at the architecture level, co-designing and influencing their future system topologies rather than merely troubleshooting legacy designs.
Design and implement robust Field-Oriented Control (FOC) frameworks.