Sr. Staff Engineer, Timing Methodology & Signoff

Ambiq Micro • Austin, TX

3d

About The Position

Ambiq is redefining what’s possible at the edge—powering next-generation AI, wearables, and IoT devices with breakthrough ultra-low-power technology. We’re looking for a Sr. Staff Engineer – Timing Methodology to take a true ownership role in driving timing from architecture to silicon—and ensuring our designs don’t just work, but excel in real-world conditions. This isn’t a “maintain the flow” role. You’ll own end-to-end timing convergence (block → SoC → post-silicon), shape methodology, flows, and signoff strategy, and work on cutting-edge FinFET, multi-patterning nodes, and unique ultra-low-power challenges. You will directly influence PPA and product success. If you thrive on solving complex timing problems others shy away from—this is your playground.

Requirements

• 8+ years of experience in timing analysis and convergence
• Deep expertise in static timing analysis (STA) using Synopsys Primetime or Cadence Tempus
• Strong experience with block-level and SoC-level timing closure in advanced nodes
• Solid understanding of digital design fundamentals and timing principles
• Hands-on experience with industry-standard EDA tools (Synopsys, Cadence)
• Proficiency in TCL, Python, or similar scripting languages
• Strong problem-solving skills and ability to drive complex issues to closure
• Excellent communication and collaboration skills across engineering teams
• Must be currently authorized to work in the United States. We are unable to sponsor or transfer visas for this role now or in the future.

Nice To Haves

• Experience with PnR tools (Fusion Compiler, Innovus)

Responsibilities

• Own timing convergence end-to-end, from methodology definition to SoC signoff
• Develop and refine timing flows, constraints, and analysis methodologies
• Drive block-level closure and SoC-level timing correlation
• Lead signoff activities, including: PVTR corner definition, Timing margining & ECO strategy, Extraction and analysis, Glitch/noise analysis & power/timing tradeoffs
• Partner cross-functionally with RTL, DFT, physical design, and IP teams
• Define and manage timing constraints across diverse IP (std cell, memory, hard IP)
• Ensure strong pre-silicon to post-silicon correlation through close collaboration with bring-up and validation teams
• Continuously enhance automation, scripts, and methodologies to improve efficiency and scalability
• Stay at the forefront of STA advancements and emerging process technologies

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed