Sr. Staff Engineer, Electrical Link Architecture

Ayar Labs • San Jose, CA

18h • Onsite

About The Position

Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co-packaged optics (CPO), we develop silicon photonics solutions that deliver unprecedented bandwidth density and reach, at a fraction of the power consumption required to scale next-generation AI models. Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Joining our Link Design and Architecture team, you will own the electrical-side modeling that drives our silicon photonics I/O platform — the analog front end, the DSP that closes the link, and the models that make circuits and photonics co-simulate end-to-end. This team is responsible for the robustness and performance of the optical links that power our technology, from component-level modeling through architecture definition, full link analysis, specification development, and yield prediction. Beyond today's products, the team drives the exploration of next-generation link architectures and directly shapes our long-term technology roadmaps.

Requirements

• MS in Electrical Engineering, Physics, or a related field.
• 5+ years (Sr. Engineer) or 8+ years (Staff Engineer) of experience in high-speed link modeling, SerDes architecture, analog/mixed-signal modeling, or DSP for wireline communication.
• Strong working knowledge of analog front-end blocks and the DSP that closes high-speed links.
• Proficiency in Verilog-A and mixed-signal simulation methodologies.
• Experience with statistical circuit analysis methods (corners, Monte Carlo).
• Strong Python skills for scientific computing and data analysis.

Nice To Haves

• Prior industry experience architecting and deploying SerDes into a shipping product.
• Ph.D.
• Hands-on experience with silicon bring-up, validation, or link characterization.
• Working knowledge of analog circuit fundamentals and high-speed signal integrity concepts.
• Familiarity with Cadence Virtuoso / ADE / Spectre.
• Familiarity with optical transceiver principles, modulation formats, and industry standards.

Responsibilities

• Build and maintain compact models of the analog front end and the DSP chain at the fidelity needed for accurate BER and link-margin prediction.
• Co-design Verilog-A models of the electrical/optical interface — modulators, photodetectors, and the blocks where circuits and photonics meet — with analog / mixed-signal (AMS) designers.
• Anchor models to silicon by working with validation engineers to reconcile simulation against measurement.
• Feed accurate electrical models into link studies, partnering with statistical link modeling experts on specs and yield using standard circuit-design methods (corners, Monte Carlo).
• Collaborate across AMS, photonics, and validation to keep the modeling stack coherent with the product roadmap.
• Run end-to-end link simulations to evaluate device and architecture choices, informing current product design and future roadmap exploration.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 101-250 employees