Sr. Staff Engineer, Analog/Mixed-signal IC Layout
About The Position
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking an exceptionally skilled and experienced Sr. Staff IC Layout Engineer, to join our Silicon Engineering team. In this senior role, you will be responsible for the physical implementation of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate is a recognized expert in the latest advanced semiconductor process nodes, capable of driving layout methodologies and ensuring the physical design meets aggressive performance, power, and area targets.
Requirements
- Associates Degree, or equivalent experience
- 10+ years of hands-on analog/mixed signal layout experience, with at least 5+ years in FinFET nodes
- A good understanding of high-speed design/layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
- Proficient with Cadence custom layout tools
- Knowledge of DRC/LVS checking flows with Calibre
Nice To Haves
- Experience with integration between custom AMS and digital components in the latest FinFET nodes.
- Some knowledge of scripting languages such as Python and SKILL.
- Previous experience laying out sensitive analog blocks such as PLLs, RF amplifiers, and high speed transmitters/receivers.
- Excellent communication skills with the ability to clearly articulate complex technical issues and solutions to cross-functional teams.
Responsibilities
- Performing physical layout for critical mixed-signal components within high speed SerDes using Cadence tools.
- Work with AMS design engineers to optimize layout for performance and reliability.
- Take part in floor planning, custom layout and verification against design rules and schematics.
- Define, develop, and implement advanced layout and verification methodologies for FinFET process technologies to maximize design efficiency. Establish and maintain layout standards, design rules, and best practices across the team.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Associate degree
