Sr Staff Electronic Design Verification Test (EDVT Engineer Hardware

Palo Alto NetworksSanta Clara, CA
$143,100 - $231,475Onsite

About The Position

About the Role We are seeking a highly skilled and motivated Senior to Principal EDVT Engineer to join our hardware engineering team. In this role, you will lead the end-to-end design verification, validation, and testing of complex electronic systems, high-speed interfaces, and power delivery networks. You will be instrumental in bridging the gap between hardware design and mass production, ensuring our products meet the highest standards of signal integrity, power integrity, and regulatory compliance. If you thrive in a fast-paced environment, love troubleshooting complex hardware anomalies, and want to own the verification strategy for next-generation hardware, we want to hear from you.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • 5+ years of hands-on experience in electronic product validation, EDVT, or hardware design engineering.
  • Deep understanding of hardware architecture, schematic design reading, and PCB layouts.
  • Expert-level proficiency with high-speed digital oscilloscopes, spectrum analyzers, protocol analyzers, logic analyzers, and digital multi-meters (DMMs).
  • Strong scripting skills in Python (or similar languages) for test automation and data analysis.
  • Proven track record of debugging complex physical-layer and system-level issues under tight timelines.
  • Exceptional verbal and written communication skills, with the ability to distill complex technical findings into actionable insights for cross-functional teams.

Nice To Haves

  • Experience with automated test frameworks and data visualization tools.
  • Familiarity with environmental testing (Thermal, Shock/Vibe) and compliance standards (EMI/EMC, Safety).
  • Experience managing or guiding junior test engineers or technicians.

Responsibilities

  • Lead the development, execution, and optimization of EDVT test plans for complex circuit boards (PCAs) and full-system hardware.
  • Perform rigorous hands-on validation of high-speed interfaces (e.g., PCIe, USB, DDR, I2C, SPI) and power delivery networks (DC-DC converters, ripple, transient response).
  • Partner closely with Hardware Design, Signal Integrity (SI), Firmware, and Component Quality teams to root-cause design issues and validate fixes.
  • Design and implement automated test setups using Python or LabVIEW to increase test coverage, repeatability, and efficiency.
  • Utilize advanced lab equipment to debug complex hardware anomalies, component failures, and unexpected system behaviors during EVT and DVT phases.
  • Collaborate with contract manufacturers (CMs) and Joint Development Manufacturers (JDMs) to transition products from prototype to mass production.
  • Author comprehensive test reports, white papers on critical design bugs, and validation summaries for executive and engineering review.

Benefits

  • Opportunities to expand your scope into hardware architecture, advanced signal integrity simulation, or engineering leadership.
  • restricted stock units
  • bonus
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