Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
About The Position
SpaceX is seeking a motivated, proactive, and intellectually curious Sr. SOC/ASIC Physical Design Engineer to join their Silicon Engineering team. This role involves developing cutting-edge next-generation silicon for Starlink, the world’s most advanced broadband internet system, which provides connectivity in places it has previously not been available, affordable or reliable. The engineer will work alongside world-class cross-disciplinary teams to expand the performance and capabilities of the Starlink network. The position focuses on the physical implementation and signoff of complex chips for space and ground infrastructures.
Requirements
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
Nice To Haves
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
Responsibilities
- Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
Benefits
- Long-term incentives, in the form of company stock, stock options, or long-term cash awards
- Potential discretionary bonuses
- Ability to purchase additional stock at a discount through an Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- Access to a 401(k) retirement plan
- Short & long-term disability insurance
- Life insurance
- Paid parental leave
- Various other discounts and perks
- 3 weeks of paid vacation
- 10 or more paid holidays per year
- 5 days of sick leave per year (for exempt employees)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
