Sr. SDE, MLA hardware/software co-design, Annapurna Labs Machine Learning Acceleration

Amazon•Bee Cave, TX

6d•$159,200 - $247,600•Onsite

About The Position

Custom machine learning chips are at the heart of our Trainium machine learning instances, and we invite you to build them with us! As a senior SDE in the pre-silicon team, you will be responsible for driving the pre-silicon hardware/software co-development for our machine learning chips. You will work with architecture, design and emulation teams to build and test our next generation AI chips. You will write bare-metal software and ML workloads to verify the end-to-end functionality and performance of the SoC. If you have a solid background in embedded software, system development or chip design, come join us!

Requirements

7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
7+ years of digital design in communication systems experience
7+ years of full-custom analog or RF layout experience
7+ years of wireless communications systems and implementation experience
8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience
7+ years of verification in communication systems experience
5+ years of UVM, C, System C, and scripting experience
3+ years of emulation experience
Bachelor's degree in Electrical Engineering or a related field
Knowledge of UVM and Matlab
Knowledge of implementing chips with multiple power islands and power gating
Knowledge of multiple access systems including OFDMA, TDMA, and CDMA
Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints
Knowledge of serial protocols including SPI, I2C, I3C, and UART
Knowledge of Python and Embedded C programming
Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering
Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2 / DVB-C, or related broadband wireless standards
Experience leading or solely developing methodology and scripts for physical synthesis
Experience taping out chips that have gone into high volume production
Experience developing products for volume production
Experience low power design techniques
Experience delivering products to volume production
Experience in modem L1/L2 algorithms development and architectures
Experience in developing link and system level simulators using MATLAB, Python, or C++
Experience in test setup automation using MATLAB, Python, or Pearl
Experience with Agile, TDD, BDD, CI, and Git
Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors
Experience leading technical initiatives and key deliverables
Experience with version control systems and CI/CD pipeline implementation
Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC

Nice To Haves

Master's degree or Ph.D. degree in Electrical Engineering or related field
Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
Experience with modern ASIC/FPGA design and verification tools
Experience with SOC bring-up and post-silicon validation

Responsibilities

Driving the pre-silicon hardware/software co-development for machine learning chips.
Working with architecture, design and emulation teams to build and test next generation AI chips.
Writing bare-metal software and ML workloads to verify the end-to-end functionality and performance of the SoC.

Benefits

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

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