Sr. RFIC Layout Designer (Starshield Silicon)

SpaceX•Hawthorne, CA

33d

About The Position

As a Sr. RFIC Layout Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs.

Requirements

Bachelor’s degree in electrical or computer engineering or 8+ years of professional experience with integrated circuit layout design in lieu of a degree
5+ years of professional experience as an IC layout designer

Nice To Haves

Strong analog layout skills
Experience in advanced node IC layouts such as 16nm, 7nm, 5nm or below
Experience in layout of circuits with frequencies up to 50GHz
Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage-controlled oscillators and mixers
Experience with skill programming
Experience with shell scripting, Perl, Python or similar language
Experience managing revision control systems
Experience with circuit design
Understanding of layout considerations for device matching, coupling and noise isolation
Working knowledge of Linux
Excellent communication skills (both oral and written) are required
Able to work independently on challenging problems

Responsibilities

Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineers to determine pad locations
Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
Work with EDA suppliers to trial new tools and features
Generate guides and demos for others in the team to showcase improvements in layout technique

Benefits

comprehensive medical, vision, and dental coverage
access to a 401(k) retirement plan
short and long-term disability insurance
life insurance
paid parental leave
various other discounts and perks
3 weeks of paid vacation
10 or more paid holidays per year
paid sick leave
company stock or long-term cash awards
potential discretionary bonuses
ability to purchase additional stock at a discount through an Employee Stock Purchase Plan