Sr. Principal Product Engineer

Cadence•San Jose, CA

9d•$216,091 - $286,000•Hybrid

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties. Lead and drive customer engagement to solve verification challenges with leading edge technologies and methodologies such as vManager. Cooperate with key customers to deploy advanced verification and debug solutions and follow up with the development groups. Discuss priorities and review functional specification for the customer requirements. Educate the field on new solution and methodologies in cooperation with the Business Unit. Understand customer challenges and drive requirements to the development teams. Understand priority, value, and timeliness of the ultimate solution. Support the development of key verification flows and methodologies to improve the Smart Verification Solutions at Cadence, focusing on the unique requirements of the design and verification community. Help develop strategy and technology roadmaps for product engineering Smart Verification flows and related applications that drive the value of the full Cadence verification suite. Write requirement specifications and review functional specifications to ensure relevant solutions are provided to customers. Some telecommuting permitted. Must be available to work on projects at various, unanticipated sites throughout the United States and internationally. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Requirements

Master’s degree in Electronic Engineering, Electrical Engineering, or related field.
Minimum eight (8) years of experience in the job offered or in a related engineering occupation.
EDA tools and verification solutions including deploying advanced verification and debugging solutions using Universal Verification Methodology (UVM)
Functional verification flows including coverage driven verification and constrained random testing
Design and verification languages and methodologies including SystemVerilog, Very High-Speed Integrated Circuit Hardware Description Language (VHDL), C/C++, Universal Verification Methodology (UVM)
Worked on verification Methodologies using vManager and UNR (Coverage unreachability)
Client and server technologies, database architectures, big data and machine learning
Building unique examples which replicate the customer scenarios, worked on the new technologies and methodologies using Powerpoint, Register-Transfer Level (RTL) design, and test bench (TB)
Must be available to work on projects at various, unanticipated sites throughout the United States and internationally.

Responsibilities

Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
Lead and drive customer engagement to solve verification challenges with leading edge technologies and methodologies such as vManager.
Cooperate with key customers to deploy advanced verification and debug solutions and follow up with the development groups.
Discuss priorities and review functional specification for the customer requirements.
Educate the field on new solution and methodologies in cooperation with the Business Unit.
Understand customer challenges and drive requirements to the development teams.
Understand priority, value, and timeliness of the ultimate solution.
Support the development of key verification flows and methodologies to improve the Smart Verification Solutions at Cadence, focusing on the unique requirements of the design and verification community.
Help develop strategy and technology roadmaps for product engineering Smart Verification flows and related applications that drive the value of the full Cadence verification suite.
Write requirement specifications and review functional specifications to ensure relevant solutions are provided to customers.