Sr. Principal Hardware Engineer

Hewlett Packard Enterprise•Sunnyvale, CA

2d•$181,000 - $367,000•Onsite

About The Position

We are seeking a highly motivated and experienced Senior Hardware Design Engineer to join our team and lead the design and development of next-generation networking hardware. The ideal candidate is a hands-on engineer with 10+ years of experience in complex hardware board design and a proven track record of taking designs from initial concept through production. This role requires deep expertise in high-speed signaling, high-power and extremely dense PCB designs, FPGA development, signal integrity analysis, thermal management using liquid cooling, and mechanical design/integration. The successful candidate will thrive in a fast-paced environment, demonstrate exceptional technical ownership, and work collaboratively across hardware, firmware, software, mechanical, thermal, and manufacturing teams.

Requirements

10+ years of hands-on hardware/board design experience with complex, high-performance electronic systems.
10+ years with the below experience as well:
Experience designing high-speed systems with 100G/200G-class signaling or comparable high-bandwidth interfaces.
Experience designing high-power, extremely dense PCBs and electronic systems.
Hands-on experience with FPGA design, including the ability to independently design and implement FPGA-based solutions when required.
Strong knowledge of Signal Integrity and Power Integrity (SI/PI) principles.
Experience with scale-up systems and high-performance computing, networking, AI/ML, accelerator, or similarly demanding architectures.
Experience with liquid cooling systems, including the development of liquid-cooled hardware and system architectures.
Excellent communication and collaboration skills with a demonstrated ability to work effectively across multidisciplinary teams.

Nice To Haves

We are looking for an engineer who combines deep technical expertise with exceptional ownership and execution.
You should be comfortable operating at both the system-architecture level and the detailed board-design level.
You are a team player with high energy, extreme focus, and a strong sense of urgency.
You take ownership, are willing to dive deep into difficult technical problems, and consistently drive projects to completion.
You should be someone who can take an ambiguous problem, define the architecture, make the necessary engineering tradeoffs, execute the design, and ultimately deliver a production-ready system.
You understand that at extreme levels of performance and density, electrical, thermal, mechanical, and system architecture cannot be designed independently.
If you are excited by challenging hardware problems involving extreme bandwidth, power, density, thermal performance (liquid cooling), we want to hear from you.

Responsibilities

Own the end-to-end hardware design lifecycle, from system architecture and concept development through schematic design, PCB layout, bring-up, validation, qualification, and production.
Lead the design of high-performance, high-density, high-power circuit boards with demanding electrical, thermal, and mechanical constraints.
Design systems incorporating high-speed serial signaling and interconnects at 100G, 200G, and beyond.
Develop and review complex schematics, power architectures, clocking solutions, high-speed interfaces, and board-level architectures.
Design and develop FPGA solutions as required, including FPGA selection, device configuration, interfaces, implementation, bring-up, and hardware/firmware integration.
Perform and/or drive Signal Integrity (SI) and Power Integrity (PI) analysis
Work on liquid-cooled scale-up system architectures, including high-bandwidth, high-performance interconnects and systems requiring significant compute, power, and bandwidth density.
Collaborate with thermal and mechanical engineering teams on liquid cooling architectures, cold plates, manifolds, flow paths, thermal interfaces, and system-level thermal solutions.
Identify technical risks early and develop practical solutions to ensure successful execution against aggressive schedules.