Eng Sr Prin - Elec

BAE Systems•Austin, TX
•$132,962 - $226,035•Hybrid

About The Position

Be part of a new age where firmware and digital design shape technological advantages on the battlefield. Help empower pilots, soldiers, and operators by developing mission‑critical systems that deliver stealth, protection, and next‑generation electronic capabilities. Join the team that protects those who protect us—at BAE Systems. We are seeking a Sr. Principal FPGA Digital Design Engineer who brings strong technical leadership, initiative, and a drive to push the boundaries of what’s possible. In this role, you will work cross‑functionally with hardware, software, and systems engineering teams, taking full ownership of high‑impact design challenges from concept through delivery, and contributing innovative solutions to problems many consider unsolvable. BAE Systems offers a modern, flexible work environment that supports work‑life balance—including a 9‑days/80‑hours pay period—and a mission‑focused culture where every design delivers real‑world impact.

Requirements

  • BS degree in Electrical Engineering or related Science, Technology, Engineering and Mathematics (STEM) major obtained by start date.
  • 8+ years VHDL/Verilog expertise.
  • Expertise in developing advanced concepts and innovative technical solutions.
  • Expertise in clock domain crossing, timing analysis, revision control.
  • Experience in hardware-software integration and validation.
  • Familiarity with Xilinx, Intel, Microchip or Lattice devices and tool flows.
  • Familiarity with the Linux environment and commands.
  • Knowledge of C programming and scripting languages such as Perl, Tcl and Python.
  • Demonstrated effective communication, collaboration, and presentation skills
  • Must be a U.S. Citizen; must be able to obtain/maintain a DoD Secret clearance

Nice To Haves

  • Advance knowledge of Digital Signal Processing
  • Experience with architecture design in Matlab/Simulink.
  • Experience with platforms as Vivado and Modelsim/QuestaSim.
  • Experience with UVM/SystemVerilog, hardware debug.
  • Experience with High-speed interfaces (PCIe).
  • Proficiency in a Linux development environment.
  • Proficiency using Git and CI/CD workflows.
  • Knowledge of software programming languages such as C/ C++.
  • Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric, and IP.
  • Previous experience related to aerospace design techniques.
  • Active DoD Secret or Top Secret clearance.

Responsibilities

  • Support program proposal development by defining technical solutions, estimating effort and budget, and collaborating with systems, hardware, and software teams to align with customer requirements.
  • Serve as an expert in advanced digital, FPGA, and system‑level design by contributing to research initiatives that develop leading‑edge concepts and establish new engineering platform solutions.
  • Translate FPGA design requirements from system‑level inputs in close collaboration with hardware, systems, and software teams to ensure seamless FPGA performance and integration.
  • Architect and implement FPGA designs across major device families (Xilinx, Intel, Microchip, Lattice) using VHDL, supporting applications ranging from gigabit‑rate serial links and RF DSP to control loops, embedded processing, and processor‑level interfaces.
  • Innovate with next‑generation FPGA platforms (Xilinx Zynq SoC, RFSoC), use SystemVerilog, UVM, and digital‑twin co‑simulation methodologies.
  • Drive synthesis, place‑and‑route, static timing analysis, and overall design optimization.
  • Build high‑quality test benches, simulation environments, and static verification setups (Lint, Autocheck, CDC, RDC).
  • Lead hands‑on lab integration, perform daily real‑time testing, and incorporate direct feedback from flight test operations and end users.
  • Support development workflows and participate in formal specification and design reviews.
  • Manage version control and configuration processes using Git/GitLab while maintaining accurate, up‑to‑date design documentation.
  • Serve as a mentor to senior and junior design engineers and help strengthen overall team technical capability.
  • Maintain full awareness of program schedules and budgets.

Benefits

  • 9‑days/80‑hours pay period
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service