Sr Principal Application Engineer
About The Position
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role involves hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff, including Synthesis, Place and Route, Design Closure, and timing/power signoff, from RTL to GDSII. The engineer will lead technical campaigns and strategies in the RTL to GDSII digital implementation space, aggressively pushing for improvements in Power, Performance, and Area (PPA). Responsibilities include delivering technical presentations, leading discussions internally and with customers, and working closely with R&D to enhance tools and methodologies. The role also supports critical customer flagship product tape outs and requires amending and augmenting flows using Tcl and/or other programming skills to meet objectives and improve results. The company is a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips. Cadence is recognized by Fortune Magazine as one of the 100 Best Companies to Work For.
Requirements
- Minimum MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 12+ years industry experience.
- Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.
- Prior experience with IC digital implementation flows and backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure, RTL to GDSII.
- Experience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must.
- Floor planning and power planning for System-on-Chip (SoC) designs with low power.
- Prior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking.
- Good hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite.
- Advanced clock tree synthesis techniques including SoC Clock Distribution, Clock Mesh, H-Tree.
- Multiple design closure including Timing, DRC, LVS, and EMIR preferred.
- Experience with advanced technology nodes including Sub 5nm and below.
Nice To Haves
- Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.
Responsibilities
- Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII.
- Lead technical campaigns and strategies in the RTL to GDSII digital implementation space.
- Aggressively push Power, Performance, and Area (PPA).
- Deliver technical presentations and lead discussions internally and with customers.
- Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.
- Support execution on critical customer flagship product tape outs.
- Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.
- Develop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA).
- Provide strong customer-facing communication and problem-solving skills.
- Demonstrate strong personal drive for continuous learning and expanding professional skillsets.
- Utilize strong verbal, written, and customer communication skills.
Benefits
- paid vacation and paid holidays
- 401(k) plan with employer match
- employee stock purchase plan
- a variety of medical, dental and vision plan options
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What This Job Offers
Job Type
Full-time
Career Level
Senior
