Sr. Packaging Engineer (TERADYNE, North Reading, MA)

Teradyne•North Reading, MA

2d•$175,300 - $280,600•Onsite

About The Position

Teradyne is seeking a Package Design Engineer with signal and power integrity experience to support advanced measurement ASIC products within the Semiconductor Test Division. This role contributes to the physical realization of complex RF, analog, digital, and mixed-signal ASIC products across the chip, package, board, socket, fixture, and system interconnect environment. The Package Design Engineer will provide technical direction for package electrical integrity strategy, package and PCB constraints, supplier design reviews, package substrate and board-level manufacturability tradeoffs, and simulation-to-hardware correlation activities.

Requirements

Master’s degree in Electrical Engineering, Packaging Engineering, or a closely related technical discipline, or equivalent experience required.
Extensive related industry experience in semiconductor package design, package and board interconnect modeling, signal integrity, power integrity, or high-speed mixed-signal hardware development.
Experience leading SI/PI design and signoff for complex package, board, and system-level interconnects used in high-performance mixed-signal, RF, serial-link, ATE, or semiconductor-test applications.
Strong knowledge of electromagnetic field theory, transmission-line theory, frequency-domain network analysis, high-speed digital signaling, analog/RF design considerations, package-to-board co-design, and power-distribution-network design.
Experience with substrate stackup definition, via and escape design, return-path management, differential and single-ended routing, power and ground assignment, bump or BGA mapping, package construction documentation, and supplier DFM rule review.
Experience with 2D and 3D electromagnetic field solvers and package or board extraction methods.
Hands-on experience using Vector Network Analyzers, TDR/TDT, high-speed oscilloscopes, probes, fixtures, and coupon structures to validate simulation models and characterize interconnect performance.
Ability to create package and PCB constraints, signoff criteria, simulation plans, correlation plans, and design-review evidence that can be used across engineering projects and cross-functional teams.
Strong technical communication, organization, and collaboration skills, including the ability to develop concise design-review materials, risk summaries, requirements documentation, and action-item tracking.

Nice To Haves

PhD or equivalent advanced technical experience preferred.
Cadence Sigrity, Clarity, Allegro/APD, Integrity/System Planner, Celsius, Allegro X/Aurora, and related Cadence tool flows are preferred.
Programming or automation experience with Python, Tcl, MATLAB, Perl, C/C++, C#, Visual Basic, or similar tools for data processing, S-parameter handling, simulation automation, test automation, or design-flow efficiency preferred.

Responsibilities

Lead ASIC package signal and power integrity architecture, including package stackup strategy, bump and BGA escape planning, return-path control, power-delivery partitioning, and package-to-board co-design.
Develop package and PCB layout constraints for high-speed serial links, clocks, DUT IO, power rails, and sensitive analog or mixed-signal interfaces while balancing electrical performance, manufacturability, cost, reliability, and schedule.
Collaborate with ASIC design, PCB design, mechanical, thermal, test, characterization, manufacturing, procurement, quality, and external package and PCB suppliers to identify and close package-related technical risks.
Build and review time-domain and frequency-domain models for package, board, socket, connector, interposer, and fixture interconnect structures, including insertion loss, return loss, crosstalk, mode conversion, skew, impedance discontinuity, and resonances.
Support package-level power distribution network planning and review activities, including target impedance, decoupling strategy, current-density review, DC IR drop, AC droop or noise behavior, plane or cavity resonance, extraction strategy, and measurement correlation.
Partner with substrate, package, PCB fabrication, assembly, and EDA tool suppliers to evaluate design rules, fabrication tolerances, assembly limitations, reliability considerations, and design-for-manufacture/design-for-assembly requirements.
Mentor engineers and contractors in package design methods, SI/PI analysis practices, modeling assumptions, design review preparation, tool workflows, and technical documentation expectations.