Sr. Manager, ML Acceleration and Performance

Rivian•Palo Alto, CA

21d

About The Position

In this role, you will lead and manage a high-caliber team within Rivian’s Perception organization. You are responsible for the end-to-end strategy of how our most advanced neural networks are compressed, optimized, and deployed onto Rivian’s custom embedded compute platforms. You will bridge the gap between high-level ML research and low-level silicon constraints, ensuring that Rivian’s autonomy stack remains "performance-first" while scaling to meet next-generation safety requirements.

Requirements

MS or Ph.D. in CS, EE, or related field with 10+ years of industrial experience, including 2+ years in a technical leadership or management capacity.
Expert-level knowledge of the ML stack: from High-level Frameworks (PyTorch) to IR/Compilers (MLIR, TVM, XLA) to Silicon (GPU/NPU/DSP).
Proven track record of deploying large-scale models into production via Quantization-Aware Training (QAT), FP8/INT4 precision, and Neural Architecture Search (NAS).
Ability to read hardware spec sheets (data sheets, ISA) and translate "Peak TFLOPS" into realistic "Application Throughput."
Proficient in C++, CUDA, and assembly-level optimization, with the ability to perform deep-dive code reviews on custom kernels.
Deep understanding of the "Elephant in the room": optimizing non-differentiable planning objectives and managing the trade-offs between open-loop and closed-loop simulation efficiency.
Mastery of system-wide profiling tools (NVIDIA Nsight, PyTorch Profiler, VTune) to identify bottlenecks across the CPU-GPU-NPU interconnects.

Responsibilities

Build, lead, and develop a world-class team of acceleration engineers.
Manage performance, set technical goals, and foster a culture of high-performance systems engineering.
Define the 2-3 year strategy for model compression (Pruning, Quantization, NAS) and runtime optimization.
Determine when to build custom in-house kernels versus leveraging vendor libraries (TensorRT, SNPE).
Act as the primary stakeholder for the Perception team when collaborating with Hardware Architecture.
Influence the design of next-gen Rivian silicon by characterizing current model bottlenecks and predicting future compute requirements.
Partner with Perception, Planning, and Embedded Systems leads to ensure that "Research" models can actually run in real-time on-vehicle without compromising safety or thermal envelopes.
Oversee the development of automated profiling and CI/CD benchmarking pipelines that track latency, memory, and energy consumption across the entire fleet.