Sr. Logic Design Engineer

Intel Corporation•Santa Clara, CA

1d•$141,910 - $200,340•Hybrid

About The Position

Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.

Requirements

RTL/Logic design using System Verilog Language
Experience with Design of Data path, Power-management flow, Arbitration logic, Clock Domain Crossing, State Machines, UPF
Experience with Front End design tools for Lint, Synthesis.
Experience with hardware simulation tools and methodologies (VCS/Verdi).
Familiarity with IP environment and configuration management tools.

Nice To Haves

UCIE PHY Design and Mixed-Signal Environment.
Cross Domain Crossing, Voltage Domain Crossings

Responsibilities

Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.