Sr. Design Verification Engineer

Credo•San Jose, CA

8d•$130,000 - $160,000

About The Position

Team Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You’ll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams. Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world. Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected].

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or related field.
7+ years of experience in RTL and functional verification using SV/UVM.
PCIe verification experience.
Experience with gate‑level simulation and firmware‑based simulation.
Proficiency in RTL design and computer architecture concepts.
Strong debugging, problem‑solving, and analytical skills.
Effective collaborator who thrives in cross‑functional teams.

Nice To Haves

Background in high‑speed connectivity solutions (PCIe/CXL, SerDes, optical DSP).
Experience working across HW/SW boundaries and with application engineering/firmware teams.
PHY verification experience.

Responsibilities

Understand design intent and develop comprehensive verification & test plans.
Develop reusable, scalable SV‑UVM testbenches and write test sequences.
Verify PCIe subsystems and other interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels (e.g., PHY, controller).
Write assertions, checkers, and coverage, analyze functional & code coverage gaps, and drive closure.
Build firmware‑based simulations in C; mirror/approximate real FW behavior to validate HW/SW interactions.
Reproduce silicon failures in simulation and perform deep debug to root cause.
Automate flows with Python/Perl/Shell scripting.
Collaborate with AEs/FW on debug, feature implementation, and spec contributions driven by DV findings.