Sr. ASIC STA Engineer

Tensordyne•Sunnyvale, CA

7d•Hybrid

About The Position

In this leadership role, you will lead ASIC physical STA design and associated engineering workflow development for Tensordyne’s multimodal generative AI inference acceleration products. As a valued senior member of our ASIC team, you will guide and assist your colleagues to help improve frontend physical design with respect to STA both the block level and full-chip within a fast-paced, agile HPC development environment that utilizes GenAI frontier models, EDA tools from external companies like Cadence/Synopsys and as well as internally developed workflows. You will drive Tensordyne’s optimization, implementation and timing exploration workflows (includes at a min. hierarchical STA, timing analysis, clock analysis) and technologies for the full ASIC chip STA flow. Your contributions will continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of Tensordyne products. This is a hands-on role that’s ideal for ASIC physical design STA experts who have a multi-disciplinary engineering background, along with a keen interest in generative AI, and a passion for designing, debugging, optimizing and finding creative EDA solutions to complex technical challenges. In this role, you will work very closely with your ASIC team members who are engaged in the design and verification of Tensordyne products, to understand and improve their workflows and EDA needs.

Requirements

10+ years of hands-on ASIC engineering experience.
Deep knowledge of VLSI/SoC chip physical design workflows.
Experience with EDA tools like Cadence/Synopsys PrimeTime/Tempus.
Strong knowledge of clock methodology and development of hierarchical constraints.
Strong physical design knowledge for STA analysis.
Ability to write SDCs for high-speed IP interfaces such as PCIe, SerDes and other multi-clock domain blocks.
Individual contributor tech lead, no direct reports initially, owning the full-chip timing closure and signoff flow.
Experience leading and supporting backend design team with understanding of STA timing issues, clock trees, routing and understanding of timing ECO generation for block level and full chip level.
Understanding of Genus/Innovus tool usage with respect to STA.
Excellent analytical, written, and verbal interpersonal skills.
Ability to productively collaborate within a global engineering team that moves at a startup pace.
Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.

Nice To Haves

Keen interest in generative AI.
Passion for designing, debugging, optimizing and finding creative EDA solutions to complex technical challenges.

Responsibilities

Lead ASIC physical STA design and associated engineering workflow development.
Guide and assist colleagues to improve frontend physical design with respect to STA at both block and full-chip levels.
Drive optimization, implementation, and timing exploration workflows for the full ASIC chip STA flow.
Innovate and improve scalable, reliable, high-performance systems and tools.
Work closely with ASIC team members to understand and improve their workflows and EDA needs.