SR ASIC Design Engineer - Networking/ DPU/ AI Systems
About The Position
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads. We are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production. We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle — from RTL architecture and design through tapeout, silicon bring-up, and mass production.
Requirements
- Seasoned ASIC design experience
- Proven hands-on experience developing high-speed, complex ASICs
- Strong experience across the complete ASIC development cycle, from RTL architecture to tapeout to mass production
- Solid background in networking and packet-processing architectures
- Experience collaborating across: Verification, Modeling, Software, Hardware/system teams
- Strong RTL design skills in: Verilog, SystemVerilog
- Strong programming skills in: C/C++
- Scripting experience in: Python, Tcl, Shell
Nice To Haves
- Experience designing complex ARM- or RISC-V-based SoC ASICs
- Hands-on experience building complex Network-on-Chip (NoC) architectures
- Strong knowledge of AXI / AMBA protocols
- Familiarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures
- Experience with post-silicon debug, bring-up, and production support
- Experience with high-performance interconnect, data movement, and SoC integration
- Self-motivated engineer with strong ownership and execution skills
- Strong problem-solving ability and willingness to take on new technical challenges
- Continuous learner who thrives in a fast-moving environment
- Excellent communication and cross-functional collaboration skills
Responsibilities
- Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads
- Contribute across the full ASIC development lifecycle: architecture definition, microarchitecture and RTL design, design reviews, implementation support, tapeout, silicon bring-up, production ramp and mass deployment support
- Collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions
- Design and implement high-speed, complex ASIC blocks for networking and data movement applications
- Work closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance
- Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases
- Contribute to performance, power, and area optimization
- Support integration of ASIC IPs into larger SoC and system architectures
- Produce high-quality design documentation and participate in technical reviews
Benefits
- AMD benefits at a glance
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What This Job Offers
Job Type
Full-time
Career Level
Senior
