Sr. Analog IC Design Engineer - IVR Architecture Team

Ferric, Inc. • New York, NY

5d • $135,000 - $170,000 • Hybrid

About The Position

As a Ferric Analog IC Design Engineer on the IVR Architecture Team, you contribute to building the most advanced cutting edge integrated voltage regulators, leveraging Ferric’s industry-leading on-chip inductor technology. These products have applications ranging from KW-scale AI processors to ultra-low power Mobile platforms including wearable devices. Your primary responsibilities include ownership of system architectures, defining specifications for system sub-blocks, and ensuring that the system design meets product target requirements.

Requirements

• MSEE with analog design experience.
• Strong knowledge of control theory and stability analysis.
• Strong knowledge of switching power converter design.
• Deep knowledge of CMOS analog circuit design, knowledge of digital circuit design.
• Experience with custom IC design flows and tools.

Nice To Haves

• BSEE + 8 years, MSEE + 5 years, or PhD + 2 years experience in power or RF IC design, or related field. Candidates demonstrating exceptional competency outside these ranges may be considered.
• Experience designing high switching frequency integrated voltage regulators.
• Experience designing ICs in standard CMOS. Exotic semiconductors are a plus.
• Deep understanding of process and device physics concepts.
• Familiarity with mixed signal verification methodologies.
• Experience with Monte Carlo analysis.
• Familiarity with analog design EDA tools such as Cadence Virtuoso, schematic capture, LVS, DRC, SPICE simulation, parasitic extraction, electromagnetics simulators.
• Experience with bench-level validation, characterization, and debug of full ICs and IC sub-systems.
• Languages: Verilog, Verilog-AMS, Python, Perl, Tcl, Cadence Skill, MATLAB, etc.

Responsibilities

• Drive system architecture design to optimize product performance targets such as efficiency, density, load current transient response, input supply rejection, and reference tracking performance for Ferric IVRs.
• Identify specifications for sub-blocks within the overall system given system level requirements.
• Maintain and implement various types of system-level models to pioneer novel power conversion and control solutions.
• Perform system-level simulations and verification with a focus on performance prediction through bench correlation.
• Design, simulation, and layout of analog IPs pertinent to IVRs as needed.
• Champion system level performance goals across design, applications, and testing teams to ensure optimal results.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior