Sr. Analog Design Engineer

Credo•San Jose, CA

1d•$120,000 - $180,000

About The Position

Credo is seeking a Sr. Analog Design Engineer for our R&D team. In this role, you will focus on IC development for our SerDes (Serializer/Deserializer) products. You will have the opportunity to work with the most advanced CMOS technology on various analog and mixed‑signal circuit blocks. The ideal candidate should have a deep understanding of analog/mixed‑signal IC design and be able to work independently. Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world. Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email [email protected].

Requirements

M.S. or Ph.D. in Electrical Engineering with emphasis on CMOS analog/mixed‑signal IC design.
5+ years of experience in IC development with advanced CMOS technology; familiarity with FinFET process.
Strong knowledge of analog/mixed‑signal circuits such as op‑amps, bandgap, regulators, comparators, equalization circuits, PLL/DLL, and phase interpolators.
Proficiency with EDA tools including Cadence Virtuoso, Synopsys Custom Compiler, MATLAB, and Verilog.
Hands‑on experience from block definition through design, simulation, layout, and verification.

Nice To Haves

Experience with SerDes system design.
Mandarin proficiency strongly preferred.

Responsibilities

Design analog and mixed‑signal blocks for SerDes technology.
Use CAD tools to run circuit simulations and analyze results.
Work with layout engineers on physical layout and perform post‑layout simulations.
Test and debug designs when silicon returns.
Prepare and maintain design documentation.