Specialist FPGA Design Engineer

L3Harris Technologies • Salt Lake City, UT

62d • Onsite

About The Position

L3Harris in Salt Lake City is actively looking for a talented FPGA (Field Programmable Gate Array) design engineer with industry experience in signal processing techniques. We design, develop, and test communication systems, advanced electronic warfare systems and multi-function systems. L3Harris development efforts include the whole lifecycle of designs from proposals, requirement definition, coding, simulation, synthesis, place and route, verification testing, and system support. This position would focus on design, HDL coding, simulation, synthesis, place and route, and lab verification. We are looking for an engineer who enjoys challenging work with a team of talented engineers and can work well both with a team and as an individual contributor. Salt Lake City provides incredible year-round outdoor recreation options and cultural experiences, and L3Harris values your work/life balance so you can enjoy these opportunities.

Requirements

• Bachelor’s Degree and minimum 4 years of prior relevant experience. Graduate Degree and a minimum of 2 years of prior related experience. In lieu of a degree, minimum of 8 years of prior related experience.
• 4+ years FPGA design experience with Digital Signal Processing designs.
• Experience in either VHDL (preferred) or Verilog hardware development languages.

Nice To Haves

• Implementation of complex Digital Signal Processing (DSP) algorithms in FPGA devices. Equivalent experience in ASIC devices is also applicable.
• Implementation of industry standard interfaces (e.g. 10/100/1000 Ethernet, SPI, UART, SDRAM, DDR3, JESD, PCIe, Ethernet).
• FPGA Design using High-speed serial interfaces (3+ Gbps)
• Git revision control
• C/C++/C# and Matlab/Simulink.

Responsibilities

• Design, HDL coding, simulation, synthesis, place and route, and lab verification of FPGAs.
• Experience in simulation, synthesis, and placement software tools such as ModelSim, Synplicity, Xilinx Vivado / ISE and/or Altera Quartus development tool sets.
• Experience in laboratory debug techniques using signal generators, digital oscilloscopes, logic analyzers, BERTS, and other complex measurement devices.
• Experience with timing closure in FPGAs.
• FPGA design experience with Digital Signal Processing designs.
• Experience in either VHDL (preferred) or Verilog hardware development languages.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level