Software Engineer III, Machine Learning Compiler, TPU Scaling

Google•Sunnyvale, CA

2d•$147,000 - $210,000

About The Position

Google software engineers develop technologies used across Google products and services, working on projects critical to the company’s needs and addressing problems across the full stack. The role is on the team developing the ML Compiler (XLA), which runs workloads on thousands of TPUs, GPUs, and other accelerators. XLA supports Google’s internal machine-learning workloads and is also used by external foundational-model producers and researchers. This position focuses on enabling the compiler to generate efficient communication on TPUs. The team develops the horizontal-scaling stack, including collective-operation lowering, communication-latency hiding, and program sharding, to help train and serve large models efficiently on TPU. The role also involves collaborating with ML performance and research teams to diagnose scaling bottlenecks and improve performance on critical workloads.

Requirements

Bachelor’s degree or equivalent practical experience.
At least 2 years of experience in low-level systems programming languages such as C++ or C.
At least 1 year of experience in one or more of the following: speech/audio, reinforcement learning, ML infrastructure, or specialization in another ML field.
At least 1 year of end-to-end machine-learning experience, such as model deployment, model evaluation, data processing, or debugging.
Experience in performance optimization and compiler development.

Nice To Haves

Master’s degree or PhD in Computer Science or a related technical field.
At least 2 years of experience with data structures and algorithms.
Experience developing accessible technologies.
Experience with hardware design or hardware architecture.

Responsibilities

Execute solutions in one or more specialized machine-learning areas, use ML infrastructure, and contribute to model optimization and data processing.
Implement and optimize collective operations (such as all-reduce, all-gather, reduce-scatter, and all-to-all) in the XLA TPU backend, from HLO-level transformations through low-level code generation.
Improve compiler scheduling to overlap communication with computation while balancing latency, memory pressure, and throughput.
Analyze current and upcoming TPU architecture and interconnect features and use them to improve scaling performance.
Work with ML performance and research teams to diagnose scaling bottlenecks and reach roofline performance on critical workloads.