SOC Top Level Physical Design Engineer, Annapurna Labs

Amazon • Cupertino, CA

1d • Onsite

About The Position

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.

Requirements

• Experience scripting with Python, Perl, Bash or PowerShell
• BS + 10yrs or MS + 7yrs in EE/CS, or related field
• 5+ in physical verification for advanced technology nodes
• Design Flow Knowledge: Understanding of backend physical design flows for chip-top/subsystems (FC/Innovus)
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
• Strong understanding of semiconductor manufacturing processes and design rules
• Proven track record of successful tape-outs
• Strong communication and collaboration abilities

Nice To Haves

• Experience in mentoring, leading, or managing more junior engineers
• Experience with integration and verification in advanced nodes [5nm or below]
• Knowledge of custom and digital design flows
• Expertise with DFM (Design for Manufacturing) methodologies
• Expertise in reliability verification (ESD, EM, IR drop)
• Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.
• Experience in extraction of design parameters, QOR metrics, and analyzing trends

Responsibilities

• Drive full chip floorplan, placement, integration, PV signoff and tapeout
• Collaborate with FE team to understand RTL and drive physical aspects early in design cycle
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator)
• Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification
• Debug and resolve physical verification issues in collaboration with layout and design teams
• Interface with foundries for MT form, rule deck updates and violation waivers; Develop and maintain verification runsets and methodologies
• Mentor junior engineers on physical verification methodologies and closure

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave
• sign-on payments
• restricted stock units (RSUs)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior