SoC Physical Integration Engineer

Advanced Micro Devices, Inc•San Jose, CA

1d•Hybrid

About The Position

AMD’s Adaptive Embedded Compute Group (AECG) builds products that blend powerful, energy-efficient processors, advanced neural engines and graphics processors, and adaptive embedded compute with programable logic to build edge computing solutions. From autonomous vehicles and industrial robotics to smart healthcare devices, AMD AECG is redefining intelligent edge computing. As a member of the SoC Physical Integration team, you'll interface with various engineering groups, including architecture, design, CAD, software, and product engineering, across various geographies to work towards the physical/electrical verification and tape out of AMD SoC FPGA/ACAP devices.

Requirements

Solid understanding of FPGA architecture
Familiarity with physical implementation with hands‑on experience using one or more industry‑standard tools Virtuoso, ICC2, FC, Innovus, or at least one of PD tools.
Strong foundational knowledge of circuit design, including hands‑on simulation experience with SPICE and Verilog
Knowledge of and/or practical experience with Place and Route (P&R) tools
Strong debugging and problem‑solving skills
Proficiency in scripting languages such as Perl, Python, TCL, C‑shell, Make, and/or other relevant scripting languages
Experience with Unix/Linux environments, including basic data management and job control
Excellent written and verbal communication skills, with the ability to collaborate effectively across teams
Bachelor’s or Master's degree in Electrical Engineering or equivalent.

Responsibilities

Defining and developing flows and methodologies for chip level integration
Developing tools for design verification or efficiency
Designing (RTL and custom), verifying, and integrating FPGA/ACAP sub-blocks
Coordinating activities between different design groups to ensure smooth integration
Executing chip level physical verification
Executing chip level electrical verification