SoC Physical Design Verification Engineer
About The Position
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You will lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Requirements
- BS or MS in Engineering (Electrical, Electronics, or related field).
- 7–14 years of hands-on experience in CPU/IP/SoC physical verification.
- Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
- Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
- Solid understanding of advanced node challenges (7nm, 5nm, 3nm) and FinFET design considerations.
- Scripting proficiency (Python, TCL) for automation and flow optimization.
- Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
- Eligibility to access U.S. export-controlled technology.
Nice To Haves
- A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
- A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
- A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
- A mentor and technical leader passionate about building efficient, manufacturable silicon.
Responsibilities
- Drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes.
- Lead physical verification closure (DRC, LVS, ERC, etc.).
- Debug issues using standard industry PV tools.
- Collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts.
- Mentor and technically lead in building efficient, manufacturable silicon.
Benefits
- Highly competitive compensation package
- Benefits
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
Associate degree
