SoC Physical Design Senior Manager, HBM

Micron • Folsom, CA

1d • Onsite

About The Position

As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.

Requirements

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
• Exposure to hierarchical physical design, top-level assembly, partitioning guidelines, and large-scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
• Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
• Ability to work in a global, cross-functional environment with strong communication and debugging skills.
• Experience implementing AI flows and using agentic AI and LLMs.

Nice To Haves

• Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 15 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

Responsibilities

• Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
• Plan project resourcing requirements and timelines.
• Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
• Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
• Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
• Drive agentic AI development initiatives and develop AI/LLM driven workflows.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree