SoC Performance Architect (Server CPU)

Qualcomm•Austin, TX

3d•$142,200 - $213,200

About The Position

We are seeking a SoC Performance Architect to lead server CPU workload analysis, performance modeling, competitive projection, and optimization across hardware and software. This role focuses on end-to-end system performance for complex server workloads, identifying bottlenecks across the compute stack, and driving actionable improvements in CPU, memory, interconnect, I/O, firmware, OS, compiler, and application behavior. The ideal candidate combines deep architectural expertise with analytical rigor and hands-on performance debugging experience. In this role, you will collaborate across architecture, design, software, systems, and partner teams to evaluate current and future SoC products, generate performance insights, and inform product and feature decisions. You will enable and analyze complex server workloads on internal platforms, build analytical and empirical models, conduct sensitivity studies, and project performance for internal and external competitive products.

Requirements

PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field
Deep understanding of CPU microarchitecture, including pipelines, out-of-order execution, branch prediction, caches, prefetching, SMT, and performance bottlenecks.
Strong knowledge of SoC architecture, including on-chip interconnect/fabric, memory controllers, DRAM systems, coherency, and I/O subsystems.
Strong understanding of OS and compiler behavior, including scheduling, memory management, synchronization, code generation, optimization, and runtime effects on performance.
Hands-on experience with industry-standard performance analysis and profiling tools.
Experience enabling and debugging complex server workloads in Linux environments.
Strong scripting and data analysis skills for handling large profiling datasets and developing performance models.

Nice To Haves

Experience with pre-silicon performance modeling, simulation, or trace-based analysis.
Familiarity with PMU-based top-down analysis, CPI decomposition, memory subsystem analysis, and sensitivity modeling.

Responsibilities

Define performance methodologies, metrics, and KPI frameworks for consistent workload tracking and feature evaluation.
Conduct hardware/software sensitivity studies.
Perform bottleneck analysis across CPU cores, cache hierarchy, memory subsystem/controllers, on-chip fabric, and I/O.
Use profiling and PMU tools to capture hotspots, call stacks, CPI breakdowns, memory behavior, and microarchitectural stall data.
Build analytical and empirical models for workload behavior, scaling, and feature sensitivity.
Develop performance projections for internal roadmap products and external competitors.
Identify and prioritize optimization opportunities; drive cross-functional execution with architecture, design, compiler, OS, firmware, and application teams.
Communicate findings, tradeoffs, and product implications to technical and executive stakeholders.