MatX is building the compute platform for AGI, developing vertically integrated full-stack solutions from silicon to systems. This role involves engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design. The engineer will partner with SubSystem owners to facilitate block integration and develop the System-On-Chip (SOC) Top-level RTL. Key responsibilities include implementing advanced automation for SOC top-level RTL integration and build processes, collaborating with the Physical Design team on floorplan connectivity, and establishing robust clock and reset methodologies. The role also involves defining and supporting SoC-level timing constraints, providing technical support to package and board teams, and ensuring alignment with chip-level floorplan connectivity requirements.
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Job Type
Full-time
Career Level
Entry Level
Education Level
No Education Listed