SoC HW (Digital, Analog or PnP) Validation Engineer

Microsoft•Hillsboro, OR

11d

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s Intelligent Cloud mission by delivering core infrastructure and foundational technologies for over 200 Microsoft online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE focuses on the design, development, manufacturing, and packaging of Microsoft's advanced computer chips, including the Azure Cobalt. The post-silicon validation team is crucial for defining and delivering operational measures of success for hardware manufacturing, enhancing planning, quality, delivery, scale, and sustainability of Microsoft cloud hardware. This role is for a SoC HW (Digital, Analog or PnP) Validation Engineer to join the post-silicon validation team, focusing on functional and/or power/performance validation for custom SoC designs.

Requirements

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Ability to meet Microsoft Cloud Background Check requirements.
Ability to provide proof of country of citizenship or US residency or other protected status for assessment of eligibility to access export-controlled information.
Verification, logic development, validation, or validation tools experience as part of a CPU, SoC and/or IP development team.
Applied understanding of Computer Architecture and CPU/SoC validation principles.
Understanding of SoC subsystem, SoC system level, and platform level functionality.
Writing scripts/software with industry standard languages like Python or C/C++.
Proficient communication, collaboration and teamwork skills.
Ability to lead, grow, and contribute to diverse and inclusive teams.
Demonstrated validation expertise in one or more of the following: Functional: Core, cache Coherency/mesh/fabric, PCIe/ IO, Memory Controller, Power Management.
Demonstrated validation expertise in Power and Performance Automation, Content Creation, or Tools/Scripts Development.
Ability to develop synthetic SoC validation Core, Coherency, Memory, and IO content to run on both bare metal and OS environments.
Ability to develop sophisticated tools/scripts to support SoC validation debug activities such as crash dumps and register dumps.
Understanding system level software and firmware.
Demonstrated success in hardware/software debug efforts.
Hands on expertise debugging silicon failures using on chip debug features (like trace or JTAG) as well as test equipment (like protocol analyzers, bit error rate testers, logic analyzers, oscilloscopes).

Nice To Haves

Experience running silicon content on pre-silicon platforms such as emulation or FPGA.

Responsibilities

Own post-silicon validation of one of the following areas - functional, electrical, or power/performance.
Define, guide, and contribute to the implementation of silicon debug tools and capabilities.
Ramp up on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software.
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise.
Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements.
Apply knowledge of validation principles and techniques to write test plans and implement them by developing test content, scripts, tools and other validation collateral.
Execute content in post-silicon, triage and debug failures.
Apply a growth mindset to learn and adapt in a complex and dynamic environment.
Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
Apply a One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.
Provide high-quality results on schedule.
Provide technical leadership with respect and integrity.
Apply expertise towards pre-silicon verification plans, tests, and debug of your area.