Soc Functional Validation Engineer

Intel•Chandler, AZ

12d•Hybrid

About The Position

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel Note: This role requires regular onsite presence to fulfill essential job responsibilities. the SoC Functional Validation Engineer: Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and system level features. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Tests interactions between various SoC features using validation infrastructure. Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness. The candidate should also exhibit the following behavioral traits: Problem-solving Strong analytical skills to address complex manufacturing challenges and develop innovative solutions. Collaboration Excellent teamwork and communication abilities. Adaptability Comfortable working in ambiguous environments. Attention to Detail.

Requirements

Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
5+ years of experience in the following areas: Working/developing test plans
Developing in a Linux/UNIX environment.
Object-oriented programming in coding any of the languages: C, C++, C#, Perl and/or Python Software.
Hardware, system bring-up, and/or silicon power-on.

Nice To Haves

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
8+ years of experience with one or more of the following: - Hardware/RTL development or debug experience, RTL debug, review Verilog code and correlate with waveform captures
- Developing test automation frameworks
- Debugging or developing fpga/emulation models
- Firmware/Software debug of large C/C++ applications, provide fixes, GitHub knowledge
Experience with design and derive testing for system clock/system reset flows.
PCIe protocol and/or PCIe interfaces testing experience.
Lab equipment (Logic Analyzers, Oscilloscopes, protocol analyzers).

Responsibilities

Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and system level features.
Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.
Reviews proposed design changes to assess impact on validation plans, tasks, and timelines.
Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis.
Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues.
Tests interactions between various SoC features using validation infrastructure.
Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing.
Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams.
Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications.
Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds).
Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness.