SOC Formal Verification Engineer, HBM

Micron Technology • Richardson, TX

3d

About The Position

The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry.
You will join a collaborative verification team focused on ensuring the functional correctness of complex system-on-chip and intellectual property designs. Your work will directly improve design quality, accelerate bug discovery, and reduce silicon risk through the use of formal verification methods. This role offers hands-on exposure to industry-standard tools, close partnership with design teams, and a strong foundation for growth in hardware verification. You will contribute to innovative computing platforms while supporting integrity, sustainability, and community-focused values.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Understanding of digital design fundamentals, including finite state machines, pipelines, handshakes, clocking, and resets.
• Familiarity with register-transfer level (RTL) design using Verilog or SystemVerilog.
• Basic knowledge of formal verification concepts such as assertions, properties, proofs, and coverage.
• Ability to work effectively in a collaborative, cross-functional engineering environment with strong analytical and problem-solving skills.

Nice To Haves

• Hands-on experience with SystemVerilog Assertions (SVA) through coursework, academic projects, or internships.
• Exposure to formal verification tools such as JasperGold, VC Formal, Questa Formal, or similar tools.
• Understanding of simulation-based verification and how formal verification complements traditional methodologies.
• Familiarity with low-power design concepts, including Unified Power Format (UPF) or Common Power Format (CPF).
• Experience with scripting languages such as Python, Tool Command Language (TCL), or shell scripting, and 1–2 years of related experience.

Responsibilities

• Debug and analyze formal counterexamples to identify root causes of functional issues in register-transfer level (RTL) designs.
• Collaborate with RTL designers, architects, and simulation-based verification engineers to resolve bugs and clarify design intent.
• Support block-level and subsystem-level formal verification, with opportunities to grow into system-on-chip (SoC)–level applications.
• Learn, apply, and help improve best practices for scalable and reusable formal verification environments.
• Contribute to verification documentation, including property descriptions, assumptions, coverage, and verification results.
• Participate in design and verification reviews, providing a correctness-focused perspective throughout the development lifecycle.
• Leveraging AI to develop AI assisted development workflows.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level