SOC Design Verification Engineer

Intel•Hillsboro, CA

4d•$164,470 - $269,100•Hybrid

About The Position

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 6 or more years of industry experience.
Master's degree in Electrical Engineering, Computer Science, or a related field with 4 or more years of industry experience.
PhD in Electrical Engineering, Computer Science, or a related field with 2 or more years of industry experience.
6+ years experience in the following: OVM/UVM methodologies and System Verilog-based constrained random verification.
Developing and executing verification test plans, including debugging and coverage closure.
Scripting languages to facilitate automation.

Nice To Haves

Extensive experience in design and/or design verification for complex IPs or SoCs.
Comprehensive understanding of the verification lifecycle, from architecture to execution and coverage closure.
Robust validation and debugging skills, with self-reliance in resolving issues with internal and external teams.
Experience in Xeon CPU Pre-Silicon or Post-Silicon Validation.
Demonstrated ability to drive continuous improvement in test suites and methodologies.
A passion for innovation and collaboration, contributing to Intel's mission to push technological boundaries and deliver impactful solutions.
Strong technical expertise in cache coherency principles for multi-processor SoCs and layered protocols such as transaction layer, data link layer, and PHY layer.

Responsibilities

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.