SoC Debug / Post-Silicon PnP Validation Engineer

Intel Corporation•San Jose, CA

2d•$105,650 - $200,340•Onsite

About The Position

Intel is seeking a motivated and detail-oriented SoC Debug / Post-Silicon PnP Validation Engineer to join our Silicon Architecture diverse team, where innovation meets execution. In this role, you will work on cutting-edge technologies, performing comprehensive power and performance validation, low-level debug tasks, and complex analysis at the SoC level for Intel products. Your expertise and contributions will help identify and resolve critical issues, improve validation methodologies, and ensure the reliability and performance of our industry-leading products. This role has a direct impact on Intel's success by driving advancements in design for debug (DFD) tools, power validation scripts, and methodologies, ultimately delivering world-class solutions that power the future of computing.

Requirements

Bachelor's degree Electrical/Computer Engineering, Mathematics or in any STEM field with 3+ years of experience. Or a Masters in the same field with 6 + months of educational or work experience.
SoC debug, validation platforms, or equivalent technical roles
Scripting languages such as Python for automation and data analysis
SoC design, architecture, and microarchitecture fundamentals
Debugging tools, defect triaging, and system-level root cause analysis

Nice To Haves

Familiarity with power management concepts, including PPM, P-states, and C-states
Experience in using power measurement tools such as NIDAQ-Intec and thermal control equipment
Knowledge of performance benchmarks and power-performance characterization methodologies

Responsibilities

Execute comprehensive power and performance (PnP) validation for systems, subsystems, and SoC-level components, applying advanced problem-solving and analytical techniques
Develop and implement innovative design for debug (DFD) tools, automation scripts, and validation strategies to optimize power and performance debug processes
Conduct thorough root cause analysis to resolve complex triage failures, power marginality issues, and performance bottlenecks, ensuring product quality and reliability
Collaborate effectively with cross-functional teams, including design engineers, validation teams, and high-volume manufacturing partners, to support SoC debug readiness and issue resolution
Formulate comprehensive debug requirements and validation strategies for new product features at the system level, ensuring alignment with architectural and performance objectives
Design, develop, and execute test methodologies to validate new device functionalities, power states, and performance characteristics while ensuring seamless integration into existing systems
Utilize advanced scripting and automation techniques to process large datasets, enabling efficient analysis and optimization of SoC power and performance metrics
Drive continuous improvement by staying current on industry trends and best practices in SoC validation, power management, and performance optimization